1. Field of the Invention
The present invention relates generally to the design of flip-chip packages used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to routing traces in a redistribution layer of an integrated circuit die.
2. Description of Related Art
A redistribution layer is a conductive metal layer formed on an integrated circuit die in which traces are formed that connect various signals and power between structures in the interior of the die and I/O pads formed on the surface of the die. Due to limitations in current integrated circuit manufacturing processes, traces wider than, for example, 12 microns and longer than 30 microns, depending on the technology, are generally slotted to maintain the trace area within a specified limit imposed by the fabrication process. Disadvantageously, the slotting layout tool typically generates design rule violations, for example, objects having a width less than the minimum width set for the redistribution layer, notches smaller than the minimum distance required between objects on the same redistribution layer, and objects on the same redistribution layer having a spacing that is less than the minimum spacing required between objects on the same redistribution layer. The design rule violations are typically detected and reported by a design rule checker (DRC) tool. Often, manual changes to the design are required to correct the errors, which increases the design cycle time and the production costs.